This application is related to co-assigned application Ser. No. 09/608,309 filed contemporaneously herewith and incorporated herein by reference.
This invention relates to methods for designing and fabricating digital circuits, and in particular to extract parasitic parameters for simulation and analysis of the circuit design in order to detect and eliminate crosstalk induced by capacitive coupling.
Before an integrated circuit is fabricated, a trial design is first analyzed by simulating the operation of the proposed circuits that are to be included within the integrated circuit. Simulation is used to verify correct functional operation of the circuit, as well as to verify correct dynamic timing operation. When two signal lines on an integrated circuit are physically adjacent there is a capacitance between the signal lines that may cause signal interference due to signal coupling.
Signal integrity is one of the key challenges in design and test, now and beyond 100 nm technologies. Rapid technology scaling is causing increased coupling capacitances due to reduced signal to signal spacing and increased distance from the substrate. Among several types of noise, crosstalk noise introduced due to parasitic coupling is predominant in digital designs. Interconnect parasitic coupling has two effects, at least. A first effect is on the delay due to different switching patterns and this affects the performance of the chip besides potential race conditions. A second effect is induced glitches or noise that could cause functional failure by switching logic-states. In the case of designs employing dynamic logic design styles, this problem is more severe due to increased noise sensitivities of pre-charged nodes. In the case of static logic, except for asynchronous signals such as preset/clear and clock nodes, a failure could result when data inputs connected to storage elements are latched during the active phase of the clock.
Design complexities are increasing with system on chip (SOC) designs and increased length of interconnect at full-chip level is one of the major sources of crosstalk noise problem. This refers to integration of system level functions, for example, many functions in a cellular telephone integrated into one integrated circuit (IC). Typically, SOC designs have CPU cores, memory blocks, logic blocks and possibly analog design blocks, all on one chip. Dynamic simulation of large designs with millions of parasitics is computationally prohibitive; in order reduce computational loads, static noise verification is used. Magnitude of the parasitic coupling, behavior of victim drivers during noise injection and dependency between factors like timing and parasitic coupling are some of key challenges in noise verification.
A commonly used simulator for designing integrated circuits is SPICE, which is available from the University of California at Berkeley, via the Department of Electrical Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets may range from several thousands to a few million, in a current typical integrated circuit design. Secondly, for each such net, several thousands of discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a RC network which could have several thousands of nodes; with each node having a resistor to the next node, a capacitor to ground, and capacitors to any adjacent signal lines.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, several thousands of increments of simulation steps are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment the SPICE program repetitively solves a matrix equation which is of the form [Y][V]=[1]. Here, Y is an n-x-n matrix, V is an nx1 matrix, and I is an nx1 matrix; where n is the number of nodes in the circuit.
For each increment in time the SPICE program makes about two-ten iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments.
Simplified models for crosstalk are described by Ashok Vittal and Malgorzata Marek-Sadowska in Crosstalk Reduction for VLSI, in IEEE Trans. on CAD, March 1997, for example. Reduced order modeling of parasitic networks is covered by Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi in PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm, in Proc. of ICCAD""97, for example. A method to account for circuit functionality during noise analysis is covered by D A Kirkpatrick and Alberto Vincentelli in Digital Sensitivity Predicting Signal Interaction Using Functional Analysis, in Proc. of ICCAD""96. A method of combining reduced order models and non-linear drivers is discussed by Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj N S in Chip-Level Verification of Parasitic Coupling Effects in Deep Sub-micron Digital Designs, in Proc. of DATE""99. Noise analysis based on noise propagation is described by Kenneth L. Shepard and Vinod Narayanan in Noise in Deep Submicron Digital Design, Tech. Dig. IEEE/ACM Int""l. Conf., Computer-Aided Design. November 1996. Methods to minimize crosstalk and crosstalk-based routing are covered by Joon-Seo Yim, Chong-Min Kyung in Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design, in Proc. of DAC 1999, for example.
Accordingly, a primary object of the present invention is to provide a method of designing circuit chips in which the time required to extract parasitic parameters is reduced and the accuracy is increased.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
Extracting parasitic parameters in a hierarchical manner forms a key aspect of the methodology of the present invention. In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals that could lead to catastrophic failures. In general, and in form the present invention, a method of fabricating an integrated circuit is provided. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative of each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines. Each cutout portion of the over the cell routing (OCR) is combined with the respective cell instance and OCR parasitic data is extracted with reference to the respective cell. For each cell instance, the intracellular parasitic data derived once for the cell is combined with the OCR parasitic information derived for that cell instance in order to form a coupled simulation model.
In another form of the invention, the operation of the integrated circuit is simulated using the coupled simulation models to determine an amount of noise induced on intercell signal lines that are routed over the cells by intracell signal lines within the cells.
In another form of the invention, an integrated circuit is fabricated according to a modified trial layout.
In another form of the invention, a computer system is provided which has a mass storage device that holds a design program for designing an integrated circuit according to the above described method.
These and other features of the invention that will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.